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S i 5 3 11
PRELIMINARY DATA SHEET
PRECISION HIGH SPEED CLOCK MULTIPLIER/REGENERATOR IC
Features
Complete precision high speed clock multiplier and regenerator device:
!
! !
Performs Clock Multiplication to One of Four Frequency Ranges: 150-167 MHz, 600-668 MHz, 1.2-1.33 GHz, or 2.4-2.67 GHz Jitter Generation as low as 0.5 psRMS for 622 MHz Output Accepts Input Clock from 9.4-668 MHz
!
! ! !
Regenerates a "Clean", JitterAttenuated Version of Input Clock DSPLLTM Technology Provides Superior Jitter Performance Small Footprint: 4 mm x 4 mm Low Power: 310 mW typical
Ordering Information: See page 22.
Applications
! ! !
MULTOUT+
!
Description
The Si5311 is a fully integrated high-speed clock multiplier and clock regenerator IC. The clock multiplier generates an output clock that is an integer multiple of the input clock. When the clock multiplier is operating in either the 150-167 MHz range or the 600-668 MHz range, the clock regenerator operates simultaneously. The clock regenerator creates a "clean" version of the input clock by using the clock synthesis phaselocked loop (PLL) to remove unwanted jitter and square up the input clock's rising and falling edges. The Si5311 uses Silicon Laboratories patented DSPLLTM architecture to achieve superior jitter performance while eliminating the analog loop filter found in traditional PLL designs. The Si5311 represents a new standard in low jitter, small size, low power, and ease-of-use for high speed clock devices. It operates from a single 2.5 V supply over the industrial temperature range (-40C to 85C).
REXT VDD GND REFCLK+ REFCLK-
20 19 18 1 2 3 4 5 6
LOL
17 16 15 PWRDN/CAL 14 VDD
GND Pad
MULTOUT-
MULTSEL1
MULTSEL0
SONET/SDH Systems Terabit Routers Digital Cross Connects
! !
Optical Transceiver Modules Gigabit Ethernet Systems Hybrid VCO Modules
Pin Assignments Si5311
GND
13 CLKOUT+ 12 CLKOUT- 11 VDD
7
VDD
8
GND
9
CLKIN+
10
CLKIN-
Top View
Functional Block Diagram
R e ge ne ratio n
BUF
2
C L K O U T+ C L K O U T-
C a libra tion
2
C L K IN + C L K IN -
BUF
D S P L L TM P h a se -L o cke d Loop
P W R D N /C A L
BUF
2
M U L TO U T+ M U L TO U T - LOL
2
2
B ia s G en
RE FCLK+ RE FCLK-
M U L TS E L1-0
REXT
Preliminary Rev. 0.6 6/01
Copyright (c) 2001 by Silicon Laboratories
Si5311-DS06
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si5311
2
Preliminary Rev. 0.6
Si5311 TA B L E O F CON T E N T S
Section Page
4 5 14 16 16 16 16 16 16 17 18 18 18 18 18 18 20 22 23 24
Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLLTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1x Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLL Lock Detection (Loss-of-Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si5311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.6
3
Si5311
Detailed Block Diagram
Regen Retime
CLKOUT+ CLKOUT-
c
CLKIN+ CLKIN-
Phase Detector
A/D
DSP n
VCO
CLK Divider
MULTOUT+
c
MULTOUT-
REFCLK+ REFCLK- 2 MULTSEL 1- 0 / REXT
Bias Generation
Lock Detector
LOL
Calibration
PWRDN/CAL
Figure 1. Detailed Block Diagram
4
Preliminary Rev. 0.6
Si5311
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature Si5311 Supply Voltage2 Symbol TA VDD Test Condition Min1 -40 2.375 Typ 25 2.5 Max1 85 2.625 Unit C V
Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated. 2. The Si5311 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 13.
V SIGNAL + Differential V ICM , V O CM SIGNAL - I/Os V IS
(SIGNAL +) - (SIGNAL -) Differential Voltage Swing V ID ,V O D Differential Peak-to-Peak Voltage t
Figure 2. Differential Voltage Measurement (CLKIN, REFCLK, CLKOUT, MULTOUT)
CLKIN
1/f MULT
MULTOUT
t CI-M t M-CO
CLKOUT
Figure 3. CLKIN to CLKOUT, MULTOUT Phase Relationship
CLKIN, REFCLK, CLKOUT, MULTOUT
80% 20% tF tR
Figure 4. Clock Input and Output Rise/Fall Times
Preliminary Rev. 0.6
5
Si5311
Table 2. DC Characteristics, VDD = 2.5 V
(VDD = 2.5 V 5%, TA = -40C to 85C)
Parameter Supply Current MULTSEL[1:0] = 00 MULTSEL[1:0] = 01 MULTSEL[1:0] = 10 MULTSEL[1:0] = 11 Power Dissipation MULTSEL[1:0] = 00 MULTSEL[1:0] = 01 MULTSEL[1:0] = 10 MULTSEL[1:0] = 11 Common Mode Input Voltage (CLKIN, REFCLK) Input Voltage Range* (CLKIN+, CLKIN-, REFCLK+, REFCLK-) Differential Input Voltage Swing* (CLKIN, REFCLK) Input Impedance (CLKIN, REFCLK) Differential Output Voltage Swing (CLKOUT) Differential Output Voltage Swing (MULTOUT) Output Common Mode Voltage (CLKOUT, MULTOUT) Output Impedance (CLKOUT, MULTOUT) Output Short to GND (CLKOUT, MULTOUT) Output Short to VDD (CLKOUT, MULTOUT) Input Voltage Low (LVTTL Inputs) Input Voltage High (LVTTL Inputs) Input Low Current (LVTTL Inputs) Input High Current (LVTTL Inputs) Output Voltage Low (LVTTL Outputs) Output Voltage High (LVTTL Outputs) Input Impedance (LVTTL Inputs) PWRDN/CAL Internal Pulldown Current
Symbol IDD
Test Condition
Min -- -- -- -- -- -- -- --
Typ 108 113 117 124 270 283 293 310 .80 VDD
"
Max 118 123 127 134 310 323 333 352 -- 750 1500 116 TBD TBD -- 116 TBD -- .8 -- TBD TBD 0.4 -- -- TBD
Unit mA
PD
mW
VICM VIS VID RIN VOD VOD VOCM ROUT ISC(-) ISC(+) VIL VIH IIL IIH VOL VOH RIN IPWRDN
See Figure 2 See Figure 2 See Figure 2 Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line Single-ended
-- -- 200 84 TBD TBD -- 84 -- TBD -- 2.0 -- --
V mV mV (pk-pk) mV (pk-pk) mV (pk-pk) V mA mA V V A A V V k A
-- -- 100 940 900 VDD - 0.7 100 25 -15 -- -- 25 25 -- -- -- 25
IO = 2 mA IO = 2 mA VPWRDN 0.8 V
-- 2.0 100 TBD
*Note: The CLKIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the positive and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In either case, the voltage applied to any individual pin (CLKIN+, CLKIN-, REFCLK+, or REFCLK-) must not exceed the specified maximum Input Voltage Range (VIS max).
6
Preliminary Rev. 0.6
Si5311
Table 3. AC Characteristics
(VDD = 2.5 V 5%, TA = -40C to 85C)
Parameter CLKIN Frequency Range CLKIN Duty Cycle REFCLK Range* REFCLK Duty Cycle REFCLK Frequency Tolerance MULTOUT Clock Rate MULTSEL[1:0] = 00 MULTSEL[1:0] = 01 MULTSEL[1:0] = 10 MULTSEL[1:0] = 11 Output Rise Time (CLKOUT, MULTOUT) Output Fall Time (CLKOUT, MULTOUT) Input Rise Time (CLKIN, REFCLK) Input Fall Time (CLKIN, REFCLK) CLKIN to MULTOUT Delay MULTSEL[1:0] = 00 MULTSEL[1:0] = 01 MULTSEL[1:0] = 10 MULTSEL[1:0] = 11 MULTOUT to CLKOUT Delay MULTSEL[1:0] = 00 MULTSEL[1:0] = 01 MULTSEL[1:0] = 10 MULTSEL[1:0] = 11 Input Return Loss
*Note: See Table 11.
*
Symbol
Test Condition
Min 9.375 TBD 9.375
Typ -- -- -- 50 --
Max 668 TBD 167 60 100
Unit MHz % MHz % ppm
CDUTY CTOL fMULT
40 -100
2400 1200 600 150 Figure 4 Figure 4 Figure 4 Figure 4 Figure 3 TBD TBD TBD TBD Figure 3 -- -- TBD TBD 100 kHz-2.5 GHz 2.5 GHz-4.0 GHz 18.7 TBD -- -- -- --
-- -- -- -- 100 100 -- --
2672 1336 668 167 TBD TBD TBD TBD
MHz
tR tF tR tF tCI-M
ps ps ps ps
0 120 150 3.4 -- -- 1/fMULT + 160 960 -- --
TBD TBD TBD TBD -- -- TBD TBD -- --
ps ps ps ns
tM-CO
ps ps dB
Preliminary Rev. 0.6
7
Si5311
Table 4. AC Characteristics (PLL Performance Characteristics)
(VDD = 2.5 V 5%, TA = -40C to 85C)
Parameter Jitter Tolerance (MULTSEL[1:0] = 00, MULTOUT = 2400 to 2672 MHz) Jitter Tolerance (MULTSEL[1:0] = 01, MULTOUT = 1200 to 1336 MHz) Jitter Tolerance (MULTSEL[1:0] = 10, MULTOUT = 600 to 668 MHz) Jitter Tolerance (MULTSEL[1:0] = 11, MULTOUT = 150 to 167 MHz) Jitter Generation (MULTOUT) (MULTSEL[1:0] = 00, MULTOUT = 2400 to 2672 MHz)* Jitter Generation (MULTOUT) (MULTSEL[1:0] = 01, MULTOUT = 1200 to 1336 MHz)* Jitter Generation (MULTOUT, CLKOUT) (MULTSEL[1:0] = 10, MULTOUT = 600 to 668 MHz)*
Symbol JTOL(PP)
Test Condition
Min
Typ
Max
Unit
See Table 5
JTOL(PP)
See Table 6
JTOL(PP)
See Table 7
JTOL(PP)
See Table 8
JGEN(rms)
Clock Input (MHz) = 600.000 to 668.000 Clock Input (MHz) = 300.000 to 334.000 Clock Input (MHz) = 600.000 to 668.000
--
TBD
TBD
psRMS
JGEN(rms
-- -- -- -- -- -- -- -- -- -- -- -- --
TBD TBD 1.9 1.2 0.9 0.5 0.5 5.8 3.2 2.2 1.4 1.3 1360
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
psRMS psRMS psRMS psRMS psRMS psRMS psRMS psRMS psRMS psRMS psRMS psRMS kHz
JGEN(rms)
Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000 Clock Input (MHz) = 300.000 to 334.000 Clock Input (MHz) = 600.000 to 668.000
Jitter Generation (MULTOUT, CLKOUT) (MULTSEL[1:0] = 11, MULTOUT = 150 to 167 MHz)*
JGEN(rms)
Clock Input (MHz) = 9.375 to 10.438 Clock Input (MHz) = 18.750 to 20.875 Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000
Jitter Transfer Bandwidth (MULTSEL[1:0] = 00, MULTOUT = 2400 to 2672 MHz)*
JBW
Clock Input (MHz) = 600.000 to 668.000
*Note: See PLL Performance section of this document for test descriptions.
8
Preliminary Rev. 0.6
Si5311
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD = 2.5 V 5%, TA = -40C to 85C)
Parameter Jitter Transfer Bandwidth (MULTSEL[1:0] = 01, MULTOUT = 1200 to 1336 MHz)* Jitter Transfer Bandwidth (MULTSEL[1:0] = 10, MULTOUT = 600 to 668 MHz)*
Symbol JBW
Test Condition Clock Input (MHz) = 300.000 to 334.000 Clock Input (MHz) = 600.000 to 668.000
Min -- -- -- -- -- -- -- -- -- -- -- -- --
Typ 680 1360 85 170 340 680 1360 21 43 85 170 340 0.03
Max TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
Unit kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz kHz dB
JBW
Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000 Clock Input (MHz) = 300.000 to 334.000 Clock Input (MHz) = 600.000 to 668.000
Jitter Transfer Bandwidth (MULTSEL[1:0] = 11, MULTOUT = 150 to 167 MHz)*
JBW
Clock Input (MHz) = 9.375 to 10.438 Clock Input (MHz) = 18.750 to 20.875 Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000
Jitter Transfer Peaking (MULTSEL[1:0] = 00, MULTOUT = 2400 to 2672 MHz)* Jitter Transfer Peaking (MULTSEL[1:0] = 01, MULTOUT = 1200 to 1336 MHz)* Jitter Transfer Peaking (MULTSEL[1:0] = 10, MULTOUT = 600 to 668 MHz)*
JP
Clock Input (MHz) = 600.000 to 668.000 Clock Input (MHz) = 300.000 to 334.000 Clock Input (MHz) = 600.000 to 668.000
JP
-- -- -- -- -- -- --
0.03 0.02 0.12 0.06 0.03 0.02 0.01
TBD TBD TBD TBD TBD TBD TBD
dB dB dB dB dB dB dB
JP
Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000 Clock Input (MHz) = 300.000 to 334.000 Clock Input (MHz) = 600.000 to 668.000
*Note: See PLL Performance section of this document for test descriptions.
Preliminary Rev. 0.6
9
Si5311
Table 4. AC Characteristics (PLL Performance Characteristics) (Continued)
(VDD = 2.5 V 5%, TA = -40C to 85C)
Parameter Jitter Transfer Peaking (MULTSEL[1:0] = 11, MULTOUT = 150 to 167 MHz)*
Symbol JP
Test Condition Clock Input (MHz) = 9.375 to 10.438 Clock Input (MHz) = 18.750 to 20.875 Clock Input (MHz) = 37.500 to 41.750 Clock Input (MHz) = 75.000 to 83.500 Clock Input (MHz) = 150.000 to 167.000
Min -- -- -- -- -- 1.45 40 TBD
Typ 0.12 0.06 0.03 0.02 0.01 1.5 60 600
Max TBD TBD TBD TBD TBD 1.7 150 TBD
Unit dB dB dB dB dB ms s ppm
Acquisition Time
TAQ
After falling edge of PWRDN/CAL From the return of valid CLKIN
Frequency Difference at which PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which PLL goes into Lock (REFCLK compared to the divided down VCO clock)
LOL
LOCK
TBD
300
TBD
ppm
*Note: See PLL Performance section of this document for test descriptions.
10
Preliminary Rev. 0.6
Si5311
Table 5. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 00, MULTOUT = 2400 to 2672 MHz)
Frequency (Hz) < TBD TBD TBD > TBD 600-668 MHz Clock Input TBD TBD TBD TBD
*Note: Measured using sinusoidal jitter at stated Test Condition frequency.
Table 6. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 01, MULTOUT = 1200 to 1336 MHz)
Frequency (Hz) < TBD TBD TBD > TBD 300-334 MHz Clock Input TBD TBD TBD TBD 600-668 MHz Clock Input TBD TBD TBD TBD
*Note: Measured using sinusoidal jitter at stated Test Condition frequency.
Table 7. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 10, MULTOUT = 600 to 668 MHz)
Frequency (Hz) < 300 25K 250K > 1M 37.5- 41.75 MHz Clock Input 25.0 2.33 0.67 0.50 75-83.5 MHz Clock Input 25.0 4.67 0.83 0.58 150-167 MHz Clock Input 25.0 9.33 1.17 0.67 300-334 MHz Clock Input 25.0 16.7 2.17 0.67 600-668 MHz Clock Input TBD TBD TBD TBD
*Note: Measured using sinusoidal jitter at stated Test Condition frequency.
Preliminary Rev. 0.6
11
Si5311
Table 8. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 11, MULTOUT = 150 to 167 MHz)
Frequency (Hz) 9.375- 10.438 MHz Clock Input TBD TBD TBD TBD TBD 18.75- 20.875 MHz Clock Input 66.7 18.0 3.33 2.67 2.00 37.5-41.75 MHz Clock Input 66.7 36.7 4.67 2.67 2.33 75-83.5 MHz Clock Input 100 66.7 8.00 3.33 2.67 150-167 MHz Clock Input TBD TBD TBD TBD TBD
< 300 6.5K 65K 325K > 1M
*Note: Measured using sinusoidal jitter at stated Test Condition frequency.
Table 9. Absolute Maximum Ratings
Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range Lead Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 k) CLKIN+, CLKIN-, REFCLK+, REFCLK-, All other pins -- -- TJCT TSTG Symbol VDD VDIG VDIF Value -0.5 to 2.8 -0.3 to 3.6 -0.3 to (VDD+ 0.3) 50 -55 to 150 -55 to 150 300 1 1.5 Unit V V V mA C C C kV kV
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 10. Thermal Characteristics
Parameter Thermal Resistance Junction to Ambient Symbol JA Test Condition Still Air Value 38 Unit C/W
12
Preliminary Rev. 0.6
Si5311
LVTTL Control Inputs Loss-of-Lock Indicator
2
MULTSEL1-0
PWRDN/CAL
Clock Input
CLKIN+ CLKIN-
CLKOUT+ CLKOUT-
LOL
Regenerated Clock
Si5311
System Reference Clock REFCLK+ REFCLK- MULTOUT+ MULTOUT- Multiplied Clock
REXT
10 k (1%)
VDD
0.1 F 2200 pF 20 pF
Figure 5. Si5311 Typical Application Circuit
Preliminary Rev. 0.6
GND
VDD
13
Si5311
Functional Description
The Si5311 is an integrated high speed clock multiplier and clock regenerator device based on Silicon Laboratories DSPLLTM technology. The DSPLL phase locks to the clock input signal (CLKIN) and generates a phase-locked output clock (MULTOUT) at a multiple of the input clock frequency. The MULTOUT output is configured to operate in the 150-167 MHz, the 600- 668 MHz, the 1.2-1.33 GHz, or the 2.4-2.67 GHz frequency range using the MULTSEL0 and MULTSEL1 control inputs. When the device is configured for a MULTOUT output frequency range of 150-167 MHz or 600-668 MHz, the DSPLL is also employed to regenerate an output clock (CLKOUT) that is a jitter-attenuated version of the input clock with clean rising and falling edges. The CLKOUT output is not characterized for the MULTOUT ranges of 1.2-1.33 GHz or 2.4-2.67 GHz. A reference clock input signal (REFCLK) is used by the DSPLL as a reference for determination of the PLL lock status. For convenience, REFCLK can be provided at any one of five frequencies, each a multiple of the CLKIN frequency. The REFCLK rate is automatically detected, so no control inputs are needed for configuration. The REFCLK input can be synchronous or asynchronous with respect to the CLKIN input. The operating ranges for the CLKIN, CLKOUT, MULTOUT, and REFCLK signals are indicated in Table 11. Values for typical applications are given in Table 12.
Table 11. CLKIN, CLKOUT, MULTOUT, REFCLK Operating Ranges
MULTSEL [1:0] CLKIN Range (MHz) 600.00-668.00 300.00-334.00 600.00-668.00 37.500-41.750 10 (MULTOUT = 600-668 MHz) 75.000-83.500 150.000-167.000 300.000-334.000 600.000-668.000 9.375-10.438 11 (MULTOUT = 150-167 MHz) 18.750-20.875 37.500-41.750 75.000-83.500 150.000-167.000 REFCLK = 2n x CLKIN 100 ppm (see Note 2) CLKOUT MULTOUT
00 (MULTOUT = 2.4-2.7 GHz) 01 (MULTOUT = 1.2-1.33 GHz)
n = -6, -5, -4, -3, or -2 See Note 1(a) n = -5, -4, -3, -2, or -1 See Note 1(a) n = -6, -5, -4, -3, or -2 See Note 1(a) n = -2, -1, 0, 1, or 2 n = -3, -2, -1, 0, or 1 n = -4, -3, -2, -1, or 0 n = -5, -4, -3, -2, or -1 n = 0, 1, 2, 3, or 4 n = -1, 0, 1, 2, or 3 n = -2, -1, 0, 1, or 2 n = -3, -2, -1, 0, or 1 n = -4, -3, -2, -1, or 0 1xCLKIN 1xCLKIN 1xCLKIN 1xCLKIN 1xCLKIN 1xCLKIN 1xCLKIN 1xCLKIN See Note 1(b)
4xCLKIN 4xCLKIN 2xCLKIN 16xCLKIN 8xCLKIN 4xCLKIN 2xCLKIN 1xCLKIN 16xCLKIN 8xCLKIN 4xCLKIN 2xCLKIN 1xCLKIN
n = -6, -5, -4, -3, or -2 See Note 1(b)
Note: 1. The CLKOUT output is not valid for (a) MULTSEL[1:0] = 00 or MULTOUT[1:0] = 01 (b) MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1 x CLKIN.) 2. The REFCLK input can be set to any one of the five CLKIN multiples indicated. The REFCLK input can be asynchronous to the CLKIN input, but must be within 100 ppm of the stated CLKIN multiple.
14
Preliminary Rev. 0.6
Si5311
Table 12. Clock Values for Typical Applications
CLKIN (MHz) SONET/SDH 9.72 19.44 38.88 77.76 155.52 311.04 622.08 REFCLK Input (MHz) 9.72 19.44 38.88 77.76 155.52 9.72, 19.44, 38.88, 77.76, or 155.52 9.72, 19.44, 38.88, 77.76, or 155.52 9.77 19.53 39.06 78.125 156.25 9.77, 19.53, 39.06, 78.125, or 156.25 9.77, 19.53, 39.06, 78.125, or 156.25 10.41 20.83 41.66 83.31 166.63 10.41, 20.83, 41.66, 83.31, or 166.63 10.41, 20.83, 41.66, 83.31, or 166.63 MULTSEL [1:0] 11 11 10 11 10 11 10 11 01 10 00 01 10 11 11 10 11 10 11 10 11 01 10 00 01 10 11 11 10 11 10 11 10 11 01 10 00 01 10 CLKOUT (MHz) 9.72 19.44 38.88 38.88 77.76 77.76 155.52 -- -- 311.04 -- -- -- 9.77 19.53 39.06 39.06 78.125 78.125 156.25 -- -- 312.5 -- -- -- 10.41 20.83 41.66 41.66 83.31 83.31 166.63 -- -- 333.26 -- -- -- MULTOUT output (MHz) 155.52 155.52 622.08 155.52 622.08 155.52 622.08 155.52 1244.16 622.08 2488.32 1244.16 622.08 156.25 156.25 625 156.25 625 156.25 625 156.25 1250 625 2500 1250 625 166.63 166.63 666.51 166.63 666.51 166.63 666.51 166.63 1333.03 666.51 2666.06 1333.03 666.51
Gigabit Ethernet
9.77 19.53 39.06 78.125 156.25 312.5 625
SONET/SDH FEC (15/14)
10.41 20.83 41.66 83.31 166.63 333.26 666.51
Preliminary Rev. 0.6
15
Si5311
DSPLLTM
The PLL structure (shown in Figure 1 on page 4) utilizes Silicon Laboratories' DSPLL technology to produce superior jitter performance while eliminating the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (VCO). The technology produces clocks with less jitter than is generated using traditional methods. In addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources. a jitter-attenuated version of the CLKIN input, resulting in a "clean" CLKOUT output with sharp rising and falling edges. The CLKOUT output is a resampled version of the CLKIN input with all CLKOUT transitions occurring synchronously with the rising edges of the MULTOUT output. The rising edges of CLKOUT are insensitive to the location of the falling edges of the CLKIN input. Thus the period of CLKOUT, measured rising edge to rising edge, is not affected by the CLKIN duty cycle or by jitter on the falling edge of CLKIN. The falling edges of CLKOUT may be affected by the location of the CLKIN falling edges as follows: If the duty cycle error of CLKIN is significant relative to the period of MULTOUT, then
1. The CLKOUT duty cycle may deviate from 50% (the falling edge of CLKOUT will be time quantized to the nearest rising edge of MULTOUT.) 2. Jitter on the falling edges of CLKIN may result in a CLKOUT duty cycle that alternates between two discrete values. Note: When the Si5310 is configured as a 1:1 multiplier, the CLKOUT output is not valid.
Clock Multiplier
The DSPLL phase locks to the clock input signal (CLKIN) and generates an output clock (MULTOUT) at a multiple of the input clock frequency. The MULTOUT output is configured to operate in the 150-167 MHz, the 600-668 MHz, the 1.2-1.33 GHz, or the 2.4-2.67 GHz frequency range using the MULTSEL0 and MULTSEL1 control inputs as indicated in Table 11. Values for typical applications are given in Table 12. The amount of jitter present in the MULTOUT output is a function of the DSPLL jitter transfer function and jitter generation characteristic. Details are provided in the PLL Performance section of this document. (See Figures 6, 7, 8, and 9.) The amount of jitter that the DSPLL can tolerate on the CLKIN input is specified in Tables 5, 6, 7, and 8. The DSPLL implementation in the Si5311 is insensitive to the duty cycle of the CLKIN input. The MULTOUT output will continue to exhibit a very good duty cycle characteristic even when the CLKIN input duty cycle is degraded.
Reference Clock
The reference clock input (REFCLK) is used to center the DSPLL and also to act as a reference for determination of the PLL lock status. REFCLK is a multiple of the CLKIN frequency, and can be provided in any one of five frequency ranges (9.375-10.438 MHz, 18.78-20.875 MHz, 37.500-41.750 MHz, 75.00- 83.50 MHz, or 150-167.00 MHz). The REFCLK rate is automatically detected by the Si5311, so no control inputs are needed for REFCLK frequency selection. The REFCLK input may be synchronous or asynchronous with respect to the CLKIN input. The frequency relationship between REFCLK and CLKIN is indicated in Table 11. In many applications, it may be desirable to tie REFCLK and CLKIN together and drive them from the same clock source. The Si5311 is insensitive to the phase relationship between CLKIN and REFCLK, so these differential inputs may be driven in phase or 180 out of phase if this simplifies board layout. Values for typical applications are given in Table 12.
1x Multiplication
The Si5311 Clock Multiplier function may also be utilized as a 1x multiplier in order to provide jitter attenuation and duty cycle correction without multiplication of the input clock frequency.
Note: When the Si5311 is configured as a 1:1 multiplier, the CLKOUT output is not valid.
DSPLL Lock Detection (Loss-of-Lock)
The Si5311 provides lock-detect circuitry that indicates whether the DSPLL has frequency locked with the incoming CLKIN signal. The circuit compares the frequency of a divided down version of the multiplier output with the frequency of the supplied reference clock. If the divided multiplier output frequency deviates from that of the reference clock by the amount specified in Table 4 on page 8, the PLL is declared out of lock, and the loss-of-lock (LOL) pin is asserted. While out of lock, the DSPLL will try to reacquire lock
Clock Regeneration
When the MULTOUT output is configured to operate in either the 150-167 MHz or the 600-667 MHz range, the Si5311 clock regeneration (CLKOUT output) is also provided. In this case, the DSPLL is used to regenerate
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Preliminary Rev. 0.6
Si5311
with the input clock. During reacquisition, the multiplier output (MULTOUT) will drift over a range of approximately 1% relative to the supplied reference clock. The LOL output will remain asserted until the divided multiplier output frequency differs from the REFCLK frequency by less than the amount specified in Table 4.
Note: LOL is not asserted during PWRDN/CAL.
the multiplier ratio desired, the larger the jitter generation. Table 4 gives the jitter generation values for specified MULTSEL0/1 settings and input clock rates.
PLL Jitter Transfer Functions (MULTSEL[1:0]=00) (dB) 0 CLKIN=622MHz -1
PLL Performance
The Si5311 DSPLL circuitry is designed to provide low jitter generation, high jitter tolerance, and a wellcontrolled jitter transfer function with low peaking. Each of these key performance parameters is described more fully in the following sections. Jitter Tolerance Jitter tolerance for the Si5311 is defined as the maximum peak-to-peak sinusoidal jitter that can be added to the incoming clock before the PLL exceeds its allowable operating range and loses lock. The tolerance is a function of the jitter frequency, the incoming clock rate, and the MULTSEL0/1 settings. The jitter tolerance for specified jitter frequencies and input clock rates is given in Tables 5, 6, 7, and 8. Jitter Transfer Jitter transfer is defined as the ratio of output signal jitter to input signal jitter for a specified jitter frequency. The jitter transfer characteristic determines the amount of input clock jitter that will be passed on to the Si5311 CLKOUT and MULTOUT outputs. The DSPLL technology used in the Si5311 provides a tightly controlled jitter transfer curve because many of the PLL gain parameters are determined by digital signal processing algorithms which do not vary over supply voltage, process, and temperature. In a system application, a well-controlled transfer curve minimizes the output clock jitter variation from board to board, providing more consistent system level jitter performance. The jitter transfer characteristic is a function of the MULTSEL0/1 settings and the input clock rate. Higher input clock rates produce higher bandwidth transfer functions with lower jitter peaking. Table 4 gives the 3 dB bandwidth and peaking values for specified input clock rates and MULTSEL0/1 settings. Figures 6, 7, 8, and 9 show a family of jitter transfer curves for different input clock rates. Jitter Generation Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock. Generated jitter arises from sources within the VCO and other PLL components. Jitter generation is a function of MULTSEL0/1 settings and input clock frequency. For clock multiplier applications, the higher
-2
-3
-4
-5
-6
-7
-8
-9 10
3
10
4
10
5
10
6
Figure 6. PLL Jitter Transfer Functions, MULTSEL[1:0] = 00 (MULTOUT = 2400-2672 MHz)
PLL Jitter Transfer Functions (MULTSEL[1:0]=01) (dB) 0 CLKIN=622MHz -1
-2
-3
-4 CLKIN=311MHz -5
-6
-7
-8
-9 10
3
10
4
10
5
10
6
Figure 7. PLL Jitter Transfer Functions, MULTSEL[1:0] = 01 (MULTOUT = 1200-1336 MHz)
Preliminary Rev. 0.6
17
Si5311
and will begin to lock to the incoming clock.
PLL Jitter Transfer Functions (MULTSEL[1:0]=10) (dB) 0 CLKIN=622MHz -1
PLL Self-Calibration
Si5311 device provides an internal self-calibration function that optimizes the loop gain parameters within the internal DSPLL. Self-calibration is initiated by a high-to-low transition of the PWRDN/CAL signal while a valid reference clock is supplied to the REFCLK input. For optimal jitter performance, the supply voltage should be stable at 2.5 V 10% when calibration is initiated. The PWRDN/CAL signal should be held high for at least 1 S after the supply has stabilized before transitioning low to initiate self-calibration. See Silicon Laboratories application note AN42 for suggested methods of generating the PWRDN/CAL signal for initiation of self-calibration.
-2
-3
-4 CLKIN=39MHz -5
-6
-7
-8
-9 10
3
10
4
10
5
10
6
Figure 8. PLL Jitter Transfer Functions, MULTSEL[1:0] = 10 (MULTOUT = 600-668 MHz)
Device Grounding
The Si5311 uses the GND pad on the bottom of the 20pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figures 12 and 13 for the ground (GND) pad location.
PLL Jitter Transfer Functions (MULTSEL[1:0]=11) (dB) 0 CLKIN=155MHz -1
Bias Generation Circuitry
The Si5311 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption compared with traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 k (1%) resistor connected between REXT and GND.
-2
-3
-4 CLKIN=9.7MHz -5
-6
-7
-8
Differential Input Circuitry
10
3
-9 10
4
10
5
10
6
Figure 9. PLL Jitter Transfer Functions, MULTSEL[1:0] = 11 (MULTOUT = 150-167 MHz)
Device Power-Down
The Si5311 PWRDN/CAL input can be used to hold the device in a power-down state when not in use. When the PWRDN/CAL input is asserted (set high), the CLKOUT and MULTOUT output drivers are disabled and the positive and negative terminals of the CLKOUT and MULTOUT outputs are each tied to VDD through 100 on-chip resistors. This feature is useful in reducing power consumption in applications that employ redundant clock sources. When PWRDN/CAL is released (set to low) the digital logic is reset to a known initial condition and the DSPLL circuitry is recalibrated
The Si5311 provides differential inputs for both the input clock (CLKIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 10. In applications where direct dc coupling is possible, the 0.1 F capacitors may be omitted. The CLKIN and REFCLK input amplifiers require input signals with minimum differential peak-topeak voltages as specified in Table 2 on page 6.
Differential Output Circuitry
The Si5311 utilizes a current mode logic (CML) architecture to output both the regenerated clock (CLKOUT) and the multiplied clock (MULTOUT). An example of output termination with ac coupling is shown in Figure 11. For applications in which direct dc coupling is possible, the 0.1 F capacitors may be omitted. The differential peak-to-peak voltage swing of the CML is listed in Table 2 on page 6.
18
Preliminary Rev. 0.6
Si5311
Clock source
Si5311 VDD
C LK IN +, R FC LK + 2.5 k
0.1 F
Zo = 50
10 k 0.1 F Zo = 50 C LK IN -, R FC LK -
2.5 k
102
10 k
GND
Figure 10. Input Termination for CLKIN and REFCLK (AC Coupled)
Si5311 VDD
100
VDD
50
CLKOUT+, 0.1 F MULTOUT+
Zo = 50
CLKOUT-, MULTOUT-
0.1 F
Zo = 50
100
VDD
50
VDD
Figure 11. Output Termination for CLKOUT and MULTOUT (AC Coupled)
Preliminary Rev. 0.6
19
Si5311
Pin Descriptions: Si5311
MULTOUT+ MULTOUT- MULTSEL1 MULTSEL0
20 19 18
REXT VDD GND REFCLK+ REFCLK-
GND
17 16 15 PWRDN 14 VDD
1 2 3 4 5 6
LOL
GND Pad
13 CLKOUT+ 12 CLKOUT- 11 VDD
7
VDD
8
GND
9
CLKIN+
10
CLKIN-
Top View
Figure 12. Si5311 Pin Configuration Table 13. Si5311 Pin Descriptions
Pin # 1 Pin Name REXT I/O Signal Level Description External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 10 k (1%) resistor. 2.5 V GND Supply Voltage. Nominally 2.5 V. Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 20-pin micro leaded package (see Figure 13) must be connected directly to supply ground. Differential Reference Clock. The reference clock sets the initial operating frequency used by the onboard PLL for clock regeneration and multiplication. Additionally, the reference clock is used as a reference in generation of the LOL output and to bound the frequency drift of MULTOUT when CLKIN is not present. Loss of Lock. This output is driven high when a divided version of the clock multiplier output deviates from the reference clock frequency by the amount specified in Table 4 on page 8. Differential Clock Input. Differential input clock from which MULTOUT is derived.
2, 7, 11, 14 3, 8, 18, and GND Pad
VDD GND
4, 5
REFCLK+, REFCLK-
I
See Table 2
6
LOL
O
LVTTL
9, 10
CLKIN+, CLKIN-
I
See Table 2
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Preliminary Rev. 0.6
Si5311
Table 13. Si5311 Pin Descriptions (Continued)
Pin # 12, 13 Pin Name CLKOUT-, CLKOUT+ I/O O Signal Level CML Description Differential Clock Output. The clock output signal is a regenerated version of the input clock signal present on CLKIN. It is phase aligned with MULTOUT and is updated on the rising edge of MULTOUT.
Notes:The CLKOUT output is not valid for MULTSEL[1:0] = 00 or MULTSEL[1:0] = 01. The CLKOUT output is also not valid for MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1x CLKIN). Connection of an improperly terminated transmission line to the CLKOUT output can cause reflections that may adversely affect the performance of the MULTOUT output. If the CLKOUT output is not used, these pins should be either tied to VDD (recommended), left unconnected, or connected to a properly terminated transmission line.
15
PWRDN/CAL
I
LVTTL
Power Down. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low. Calibration. To initiate an internal self-calibration, force a highto-low transition on this pin. (See "PLL Self-Calibration" on page 18.)
Note: This input has a weak internal pulldown.
16, 17
MULTOUT-, MULTOUT+
O
CML
Differential Multiplier Output. The multiplier output is generated from the signal present on CLKIN. In the absence of CLKIN, the REFCLK is used to bound the frequency of MULTOUT according to Table 4 on page 8.
Note: Connection of an improperly terminated transmission line to the MULTOUT output can cause reflections that may adversely affect the CLKOUT output. If the MULTOUT output is not used, these pins should be either tied to VDD (recommended), left unconnected, or connected to a properly terminated transmission line.
19
MULTSEL1, MULTSEL0
I
LVTTL
Multiplier Rate Select. These pins configure the onboard PLL-based clock multiplier for clock generation at one of four user selectable clock rates.
Note: These inputs have weak internal pulldowns.
20
NC
No Connect. This pin should be tied to ground.
Preliminary Rev. 0.6
21
Si5311
Ordering Guide
Table 14. Ordering Guide Part Number SI5311-BM Package 20-pin MLP Temperature -40C to 85C
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Preliminary Rev. 0.6
Si5311
Package Outline
Figure 13 illustrates the package details for the Si5311. Table 15 lists the values for the dimensions shown in the illustration.
TO P VIEW
A D D /2 D1 10 0 .0 5 A A1 D 1 /2 2X N 0 .2 5 C B 4X P 5 6 0 .5 0 D IA . 1 2 3 E1 E 4X Q E 1 /2 E /2 1 2 3 E2 (N e-1 )X e REF. A2 A3 N C 4X P b R D2 D 2 /2 8. 4 0 .1 0
M
2X 0 .2 5 C A
BO TTO M VIEW
CA B
L 0 .2 0 2X C B B 0 .2 0 2X b A1 11 C A 0 e S E A T IN G PLANE (N d -1 )X e REF.
E 2 /2
C
4 C C L C C L
NO TES: 1. 2. 3. DIE THICKNESS ALLO W ABLE IS 0.305mm MA XIMUM(.012 INCHES MAXIMUM ) DIMENSIO NING & TO LERANCES CO NFO RM T O ASME Y14.5M. - 1994. N IS THE NUMB ER O F TERMINALS. Nd IS THE NUM BER O F TERMINALS IN X-DIR ECTIO N & Ne IS THE NUM BER O F TERMINALS IN Y-DIR ECTIO N. DIMENSIO N b A PPLIES TO PLATED TERMINA L AND IS MEASURED BETW EEN 0.20 AND 0.25mm FRO M TERMINA L TIP. THE PIN #1 IDE NTIFIER MUST BE EXISTED O N THE TO P SURFACE O F THE PACKAG E BY U SING INDENTATIO N MARK O R O THER FEATURE O F PACKA G E BO DY. 6. 7. 8. 9. 10. EXACT SHAPE AND SIZE O F THIS FEATURE IS O PTIO NAL. ALL DIMENSIO N S ARE IN MILLIMETERS. THE SHAPE SH O W N O N FO UR CO RNERS AR E NO T ACTUAL I/O . PACKAG E W AR PAG E MAX 0.05mm. APPLIED FO R E XPO SED PAD AND TERMINAL S. EXCLUDE EMB EDDING PART O F EXPO SED PAD FRO M MEA SURING . 11. APPLIED O NLY FO R TERMINALS.
SEC TIO N "C -C "
SCALE: NONE
e
e
4.
T E R M IN A L T IP
5.
FO R EVEN TER M IN AL/SID E
FO R O D D TER M IN AL/SID E
Figure 13. 20-pin Micro Leaded Package (MLP) Table 15. Package Diagram Dimensions Symbol A A1 A2 A3 b D D1 D2 e E Min -- 0.00 -- 0.18 Millimeters Nom 0.85 0.01 0.65 0.20 REF -- 4.00 BSC 3.75 BSC 2.10 0.50 BSC 4.00 BSC Max 1.00 0.05 0.80 0.30 Symbol Min E1 E2 N Nd Ne L P Q R 1.95 Millimeters Nom 3.75 BSC 2.10 20 5 5 0.60 0.42 0.40 0.17 -- Max 2.25
1.95
2.25
0.50 0.24 0.30 0.13 --
0.75 0.60 0.65 0.23 12
Preliminary Rev. 0.6
23
Si5311
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Preliminary Rev. 0.6

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